(1) Field of the Invention
This invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a synchronous or asynchronous operation mode for an external clock.
(2) Description of the Related Art
To reduce the power consumption of a semiconductor memory, such as a dynamic random access memory (DRAM), including an internal (step-up or step-down) power supply circuit for generating internal power supply voltage, the internal power supply circuit has traditionally been controlled optimally according to the operating state of the semiconductor memory.
To be concrete, a step-up potential detection circuit activated continuously or at activation time is located for making a step-up circuit for raising the voltage of a word line operate optimally in the active or standby state of the semiconductor memory.
With recent portable devices, a further reduction in power consumption is required. A semiconductor memory having not only the above operation mode but also a power-down mode in which the generation of internal power supply voltage by an internal power supply circuit is stopped for reducing power consumption is disclosed (see, for example, Japanese Unexamined Patent Publication No. 2003-162895).
In addition, to increase efficiency in data transfer, a synchronous mode in which data synchronizes with an external clock is required. Therefore, there is great necessity for the development of a semiconductor memory having a power-down mode, a synchronous mode, and an asynchronous mode as operation modes.
FIG. 6 is a state transition diagram of a semiconductor memory having a power-down state and synchronous and asynchronous operation modes for an external clock.
As shown in FIG. 6, when external power supply voltage is applied to a semiconductor memory (power-up state T10), the semiconductor memory goes into a standby state T12 in an asynchronous mode after the elapse of pause time T11.
The semiconductor memory makes the transition from the standby state T12 to a power-down state T13 in the asynchronous mode by making a transition signal ce2 inputted from a chip enable terminal CE2 (CE2 terminal) described later low potential (“L” or “L” level). As is not shown, the semiconductor memory can make the transition from the standby state T12 to an active state in the asynchronous mode (asynchronous operation, such as read, write, or erase).
Moreover, the semiconductor memory can make the transition (return) from the power-down state T13 in the asynchronous mode to the standby state T12 in the asynchronous mode by making the transition signal ce2 high potential (“H” or “E” level).
When a synchronous mode is set in the standby state T12 in the asynchronous mode by making a signal a15z, being one of CR setting commands described later, “H” (control register (CR) setting state T14 to the synchronous mode), the semiconductor memory makes the transition to a standby state T15 in the synchronous mode. On the other hand, when an asynchronous mode is set in the standby state T15 in the synchronous mode by making the signal a15z “L” (CR setting state T14 to the asynchronous mode), the semiconductor memory makes the transition to the standby state T12 in the asynchronous mode.
By making the transition signal ce2 “L,” the semiconductor memory makes the transition from the standby state T15 in the synchronous mode to a power-down state T16 in the synchronous mode. As is not shown, the semiconductor memory can make the transition from the standby state T15 to an active state in the synchronous mode (synchronous operation, such as read, write, or erase).
By making the transition signal ce2 “H,” the semiconductor memory can make the transition from the power-down state T16 in the synchronous mode to the standby state T15 in the synchronous mode.
FIG. 7 shows the structure of a mode register which enables the state transitions shown in FIG. 6.
A mode register 50 includes a state selection section 51 and a synchronous/asynchronous mode setting section 52.
The state selection section 51 accepts a CR setting command from a control register (not shown), accepts the transition signal ce2 for selecting a state from the CE2 terminal, and selects the standby state T12 or T15, the power-down state T13 or T16, or the active state, such as read, write, or erase.
In the standby state T12 or T15, the synchronous/asynchronous mode setting section 52 generates a state transition signal burstx for making the transition between the synchronous and asynchronous modes possible on the basis of the signal a15z, being one of the CR setting commands, sent from the control register (not shown) and information indicative of a state selected by the state selection section 51 and sends it to the outside.
Traditionally, the transition to a power-down state has been made only from the asynchronous mode or, as shown in the state transition diagram in FIG. 6, only within the synchronous operation mode or the asynchronous operation mode. That is to say, the transition from a power-down state can be made only within a (synchronous or asynchronous) operation mode set in advance. Accordingly, to make the transition from a power-down state, the state transition signal burstx is generated by the mode register 50 shown in FIG. 7 on the basis of the transition signal ce2 inputted from the CE2 terminal.